Education                                                                                                                                  

                                                                                                                      

● Ulsan National Institute of Science and Technology, Ulsan, Korea                   2015 – 2020

Combined M.S. and Ph.D. in Electrical Engineering

 

● Ulsan National Institute of Science and Technology, Ulsan, Korea                   2010 – 2015

B.S. in Electrical and Computer Engineering, magna cum laude

 

 

Publications                                                                                                                                                                                                                                                 

                                                                                                

● S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi, "An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier with a Multiplication Factor of 114," IEEE Journal of Solid-State Circuits, Apr. 2019, invited from IEEE 2018 Symp. VLSI Circuits.

 

● S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi, "A 140fsRMS-Jitter and −72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb. 2019, accepted for presentation.

 

● S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi, "153 fsRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier," IEEE Symposium on VLSI Circuits Dig., Jun. 2018.

        

●  J. Lee, S. Choi, Y. Cho, and J. Choi, "A linearly frequency-tunable and low-phase noise ring VCO using varactors with optimally-spaced bias voltages," IET Electronics Letters, Mar. 2018.

 

●  S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi, "A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier with an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers," IEEE Journal of Solid-State Circuits, Jan. 2018.

 

● S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee and J. Choi, “Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers”, IEEE 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2018.

 

● S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi, "A PVT-Robust 29GHz Injection-Locked Frequency Multiplier with a 600uW Frequency-Tracking Loop for mm-Band 5G Transceivers," IEEE International Solid-State Circuit Conference (ISSCC) Dig. Tech. Papers, Feb. 2017.

 

● S. Choi, S. Yoo, Y. Lim, and J. Choi, "A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier with a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector," IEEE Journal of Solid-State Circuits, Aug. 2016. 

 

● S. Choi, S. Yoo, and J. Choi, "A 185-fsrms Integrated-Jitter and –245-dB FOM PVT-Robust Ring-VCO-Based Injection-Locked Clock Multiplier," IEEE International Solid-State Circuit Conference (ISSCC) Dig. Tech. Papers, Feb. 2016.

 

● S. Yoo, S. Choi, T. Seong and J. Choi, "An Ultra-Low Power and Compact LC-Tank-Based Frequency Tripler Using Pulsed Input Signals", IEEE Microwave and Wireless Components Letters (MWCL), Feb. 2016.

 

● M. Kim, S. Choi, and J. Choi, "A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-time PVT-Calibrator with Replica-Delay Cells," IEEE Journal of Solid-State Circuits, Feb. 2016.

 

● M. Kim, S. Choi, and J. Choi, "A 450-fs jitter PVT robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells", IEEE Symposium on VLSI Circuits Dig., Jun. 2018, Jun. 2015.

 

 

Granted Patents                                                                                                                       

                                                                                                             

● J. Choi, S. Yoo, and S. Choi, Apparatus and Method for Injection-Locked Frequency Multiply, Patent No.: 10-1833163, Feb. 21, 2018. (Granted)

 

● J. Choi, S. Choi, and S. Yoo, Injection Locked Clock Multiplication Apparatus and Method Using a Replica Delay Cell, Patent No.:10-1724365, Apr. 3, 2017. (Granted)

 

Filed Patents

                                                                                                              

●  J. Choi, S. Choi, and S. Yoo, PVT-Robust Ring-LC-Hybrid ILCM Using a Dual-Purpose Frequency Calibrator, Application No.:10-2018-0049307, Apr. 27, 2018. (Filed)

 

 

Awards and Honors                                                                                                                 

                                                                                                

● 19th Korea Semiconductor Design Competition, Presesident of Semiconductor Association's Award, Oct. 2018

 

● 25th Samsung HumanTech Paper Award, Silver Prize in Circuit Design, Feb. 2018.

 

● 24th Samsung HumanTech Paper Award, Bronze Prize in Circuit Design, Feb. 2018.

 

● 23rd Samsung HumanTech Paper Award, Bronze Prize in Circuit Design, Feb. 2017.

 

● IEEE International Solid-State Circuit Conference (ISSCC) Silkroad Award, Feb. 2017.

 

● 22nd Samsung HumanTech Paper Award, Silver Prize in Circuit Design, Feb. 2016.

 

● Global Ph.D. Fellowship, Mar. 2016