Publications

J. Kim, Y. Jo, S. Min, J. Chun, Y. Shin, H. Song, S. Kwak, K. Park*, and J. Choi*, "A 16.8–33.6Gb/s, 0.93pJ/b Direct-Frequency-Tracking Digital CDR with an SSC Profile Replicator for Per-Lane Data-Rate Variation and High Jitter Tolerance under Deep SSC," IEEE Symp. VLSI Circuits Dig., Accepted.

M. Han=, J. Kim=, H. Song, and J. Choi*, "A Comprehensive Power-Supply-Induced Jitter Mitigation Scheme for HBM Interfaces Using a Strobe-Triggered Digital LDO and Local Replica Regulators Achieving 10.7mV Voltage Droop and 1.4ns Settling Time," IEEE Custom Integrated Circuits Conference (CICC), Accepted. (= Equally-Credited Authors)

J. Kim=, M. Han=, H. Song, J. Bang, Y. Lim*, and J. Choi*, "A Command-Aware Hybrid LDO with Ultra-Small Voltage Droop and Fast Settling Time for Power-Supply-Induced Jitter Mitigation in HBM Interfaces," IEEE J. Solid-State Circuits (JSSC), Jan. 2026. (= Equally-Credited Authors)


Awards

26th Korea Semiconductor Design Competition, Corporate Special Award, Oct. 2025.