Publications
J. Kim, Y. Jo, S. Min, J. Chun, Y. Shin, H. Song, S. Kwak, K. Park*, and J. Choi*, "A 16.8–33.6Gb/s, 0.93pJ/b Direct-Frequency-Tracking Digital CDR with an SSC Profile Replicator for Per-Lane Data-Rate Variation and High Jitter Tolerance under Deep SSC," IEEE Symp. VLSI Circuits Dig., Accepted.

S. Lee=, S. Jung=, S. Kwak, S. Lee, H. Lee, and J. Choi*, "An 85.5-to-94.5-GHz W-Band Fully-Symmetric Quadrature LO Generator with a Fast Quadrature Calibration Technique, Achieving Closely Matched 61-fs RMS Jitter and 41-dB IRR," IEEE RFIC Symposium, Accepted. (= Equally-Credited Authors) 

Awards
26th Korea Semiconductor Design Competition, Corporate Special Award, Oct. 2025.