Publications

Y. Shin, J. Kim, J. Lee, Y. Jo, and J. Choi*, "A Low-Jitter Fractional-N Sampling PLL with Voltage-Domain Quantization-Error Cancellation Using a Nonlinearity-Replication Technique," IEEE J. Solid-State Circuits (JSSC), Accepted.

J. Lee=, C. Hwang=, J. Seo and J. Choi*, "A Versatile On-Chip Jitter Measurement Circuit with Dynamic Quantizer-Resolution Adaptation for Arbitrary Clocks across 1–8GHz and 20–130pspp Jitter," IEEE Symp. VLSI Circuits Dig., Accepted. (= Equally-Credited Authors)

Y. Shin, Y. Jo, J. Kim, J. Lee, J. Kim, and J. Choi*, "A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces," IEEE J. Solid-State Circuits (JSSC), accepted for publication.

Y. Shin=, J. Lee=, J. Kim=, Y. Jo, and J. Choi*, "A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024. (= Equally-Credited Authors)

Y. Shin=, Y. Jo=, J. Kim, J. Lee, J. Kim, and J. Choi*, "A 900μW, 1–4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)

Awards

32nd Samsung Humantech Paper Award, Honorable Mention Award in Circuit Design, Feb. 2026.

26th Korea Semiconductor Design Competition, Presidential Award, Oct. 2025.

25th Korea Semiconductor Design Competition, Corporate Special Award, Oct. 2024.

30th Samsung Humantech Paper Award, Silver Award in Circuit Design, Feb. 2024.

24th Korea Semiconductor Design Competition, Minister Award (3rd place), 2023.11.7